Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide input/output communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package.
The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and printed wiring board (PWB) and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder ball of the controlled collapse chip connection, also known as “C4”, connections. It is therefore important to mitigate the substantial stress caused by thermal cycling as temperatures within the device change during operation.
CTE mismatch is indeed a concern. However, a second primary source of thermal cycling concerns the stresses encountered in the assembly of the chip to the packaging substrate. During this process, the solder ball must be heated and softened by reflow so that it can join the chip to the solder pad on the substrate. During cool-down of the chip-join process, considerable vertical tensile and shear stresses are translated through the solder ball to the underlying chip-level wiring. These stresses can cause the physical breakage of dielectric and wiring levels. These stresses can be a greater threat to proper chip functioning than the stresses discussed the paragraph above.
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a substrate (e.g., a ceramic substrate or a plastic composite substrate). Such a semiconductor chip package is usually intended for mounting on a printed circuit card or board. In the case of a ball grid array (BGA) package, the chip carrier includes a second circuitized surface opposite the surface to which the chip is attached. This, in turn, is connected to the printed circuit card or board. Chip carriers of this type provide a relatively high density of chip connections and are readily achieved by mounting one or more semiconductor chips on the circuitized surface of a chip carrier substrate in the so-called “flip chip” configuration.
Another type of attachment is called direct chip attach (DCA). For direct chip attach, individual IC chips are mounted on the cards or boards. The space between the mounted chip and the card or board is then filled with an epoxy resin. By this expedient, the standoff between the IC chip and the card or board is encapsulated with epoxy.
However, one problem encountered with the combination of DCA and C4 bonding is the difficulty of reworking the encapsulated package. In order to improve rework and to accommodate the CTE mismatches between the chip and the PWB, many prior art proposals have been developed to connect integrated circuit chips to printed wiring boards via an intermediate element. Often, chip carriers are interposed between the chip and the circuit board; the CTE of the chip carrier is itself chosen as some intermediate value to provide a reasonable match to both the chip and to the printed circuit board. The very large difference in CTE between the silicon device and the printed circuit board generally requires some intermediate device carrier to reduce localized delamination or white bumps. One such type of interconnection mounts the integrated circuit chip on a ceramic chip carrier or module, which module is mounted on a circuit board. One or more chips may be mounted on each device carrier or module, and one or more modules may be mounted on any given circuit board. In a particularly well known type of configuration, the integrated circuit chip is mounted onto a ceramic module by flip chip bonding wherein the I/O pads on the face of the chip are bonded to corresponding pads on the module. Such connections are formed by solder bumps or solder balls normally using solder reflow techniques. It is these connections that are referred to as C4 connections.
FIG. 1 is a top view of a prior art metal pad 100 for a solder bump interconnection. The metal pad 100 has final passivation opening 102 of 47 um and via in hard dielectric passivation connection 101 of 64 um.
FIG. 3 is a side perspective view of the prior art of FIG. 1. Metal pad 300 has a solder bump 301 according to C4 technology. The solder bump 301 is lead free and preferably a SnAg Pb-free solder. Below the solder bump 301 is a ball limiting metallurgy 302. Below the ball limiting metallurgy 302 is final passivation opening/layer 303 of approximately 47 um containing photosensitive polyimide which is over aluminum pad level 304. Below the aluminum pad 304 is the via and electrical connection opening 305 of approximately 64 um. Below the TV opening 305 is the last copper wiring level 306. The via 307 lies directly below the last metallization level 306. Finally, copper pads/wires level 308 is provided to make circuitry connections. For purposes of comparison, the relative stress level in the oxide under the last metallization level 306 in dashed boxes 309, 309′ and 309″ for this configuration is 1 where values greater than 1 have higher stress and values below 1 have lower stress. The areas 309, 309′ and 309″ represent high stress areas under the photosensitive polyimide edge in the prior art.